Technology.am (Aug. 25, 2009) — TSMC has been working to develop high-k metal gate technologies for low power applications. TSMC added a low power process to its 28nm high-k metal gate (HKMG) road map. Now TSMC has become the first foundry not only to achieve 28nm functional 64Mb SRAM yield, but also to achieve it across all three 28nm nodes.
The 28nm HPL process is considered suitable as a SoC platform for general market applications. It is differentiated from the 28LP technology, which is positioned for cellular and handheld applications where lower cost and faster time-to-market from an evolutionary SiON process is most attractive.
This accomplishment shows that TSMC is not only able to extend conventional SiON technology to 28nm, but is also able to deliver the right 28nm HKMG technology at the same time.
The 28nmHPL (Low Power with HKMG) process supports low power, low leakage, and medium-high performance on a gate-last approach.
The TSMC 28nm development and ramp-up has remained on track since the announcement made in September of 2008. The 28LP process is expected to enter risk production at the end of Q1 of 2010, followed closely by the 28HP risk production at the end of Q2 and the 28HPL risk production in Q3.
The 28nm LP process will serve as a fast time-to-market and low cost technology ideal for cellular and mobile applications.
The 28nm HP process is expected to support devices such as CPUs, GPUs, Chipsets, FPGAs, networking, video game consoles, and mobile computing applications that are performance demanding.
The 28nm HPL process features low power, low leakage, and medium-high performance. It is aimed to support applications such as cell phone, smart netbook, wireless communication and portable consumer electronics that demand low leakage.